Static random access memory (“SRAM”) arrays are commonly used for storage on integrated circuit devices. As semiconductor processes advance, device sizes and power-supply levels both continue to fall. Falling device sizes results in reduced charge storage in the SRAM cells. The reduced charge storage results in increasing soft error rate (“SER”). SER is caused by alpha-particles and cosmic ray neurons that cause errors in stored bits. SER has become a major concern as SRAM cells are implemented in advanced semiconductor processes recently, because the SER, if uncorrected, leads to a failure rate that is higher than the failure rate for all other mechanisms, combined.
A circuit approach to reducing SER is to add on-chip error correction circuitry (“ECC”). While the ECC architectures can reduce the SER, these approaches increase chip size and decrease the speed of the SRAM accesses.
Recent advances in finFET transistor technology have made advanced SRAM cells using finFET transistors possible. In contrast to the prior planar MOS transistor, which has a channel formed at the surface of a semiconductor substrate, a finFET has a three dimensional channel region. In the finFET, the channel for the transistor is formed on the sides, and sometimes also the top, of a “fin” of semiconductor material. The gate, typically a polysilicon or metal gate, extends over the fin and a gate dielectric is disposed between the gate and the fin. The three-dimensional shape of the finFET channel region allows for an increased gate width without increased silicon area even as the overall scale of the devices is reduced with semiconductor process scaling; and in conjunction with a reduced gate length; providing a reasonable channel width characteristic at a low silicon area cost.
However, when an SRAM cell is formed using single fin finFET transistors for the pull up or “PU” transistors and also the pass gate “PG” transistors, both n-wells and p-wells are used. In a conventional SRAM cell with single fin finFET transistors, the p-well region is always larger than the n-well region by at least 20%. This is due to the n-type finFET transistors being at least twice the p-type finFET gate count. The collection area for alpha particles is high and this will lead to additional SER increases.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.